ICS93718 查看數據表（PDF） - Integrated Device Technology
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ICS93718 Datasheet PDF : 9 Pages
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ICS93718
DDR and SDRAM Buffer
Pin Description
PIN NUMBER
PIN NAME
1
FB_OUT
2, 8, 12, 17, 23, VDD3.3_2.5
3, 9, 14, 18, 26,
31, 35, 40, 46
GND
45, 43, 39,
34, 30, 28,
DDRT (11:6)
44, 42, 38,
33, 29, 27,
DDRC (11:6)
21, 19, 15, 10, 6, 4
DDRT (5:0)
SDRAM (10, 8, 6, 4, 2, 0)
DDRC (5:0)
22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3,
1,)
13
BUF_IN
24
25
32, 37, 41, 47
SDATA
SCLK
VDD2.5
36
PD#
48
SEL_DDR
TYPE
DESCRIPTION
OUT
PWR
Feedback output, dedicated for external feedback
2.5V or 3.3V voltage supply to pins
4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22
PWR Ground
OUT "True" Clock of differential pair outputs.
OUT "Complementory" clocks of differential pair outputs.
OUT
"True" Clock of differential pair outputs, or 3.3V SDRAM
clock outputs depending on SEL_DDR input
OUT
"Complementory" clocks of differential pair outputs, or 3.3V
SDRAM clock outputs depending on SEL_DDR input
IN Single ended buffer input
I/O Data pin for I2C circuitry 5V tolerant
IN Clock input of I2C input, 5V tolerant input
PWR
IN
IN
2.5V voltage supply
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled. The latency of the power down will not be greater
than 3ms.
Select input for DDR mode or DDR/SD mode
0=DDR/SD mode 1=DDR mode
IDTTM/ICSTM DDR and SDRAM Buffer
ICS93718 REV E 02/11/07
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