PI6C185-00 查看數據表（PDF） - Pericom Semiconductor Corporation
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PI6C185-00 Datasheet PDF : 7 Pages
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PI6C185-00
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788P9900r1122e33c44i55s66i77o8899n001112233-4475566C778899lo0011c22k112233B4455u6677f88f99e00r1122
DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C)
Symbol
Parameter
Test Condition
Input Voltage
VIH
Input high voltage
VIL
Input low voltage
IIL
Input leakage current
VDD
0 < VIN < VDD
VDD[0-9] = 3.3V ±5%
VOH
Output high voltage
IOH = –1mA
VOL
COUT
CIN
LPIN
TA
Output low voltage
Output pin capacitance
Input pin capacitance
Pin Inductance
Ambient Temperature
IOL = 1mA
No Airflow
Min.
Max.
Units
2.0
VDD +0.3
V
VSS -0.3
0.8
-5
+5
mA
2.4
V
0.4
6
pF
5
7
nH
0
70
°C
SDRAM Clock Buffer Operating Specification
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
IOHMIN
Pull-up current
VOUT = 2.0V
–54
IOHMAX
Pull-up current
VOUT = 3.135V
-46
IOLMIN
Pull-down current
VOUT = 1.0V
54
IOLMAX
Pull-down current
VOUT = 0.4V
53
trhSDRAM Output rise edge rate SDRAM only 3.3V ±5% @04V-2.4V
1.5
4
tthSDRAM Output fall edge rate SDRAM only 3.3V ±5% @2.4V-0.4V
1.5
4
Units
mA
V/ns
AC Timing
Symbol
Parameter
tSDKP
tSDKH
tSDKL
tSDRISE
tSDFALL
tPLH
tPHL
tPZL,tPZH
tPLZ,tPHZ
Duty Cycle
tSDSKW
SDRAM CLK period
SDRAM CLK high time
SDRAM CLK low time
SDRAM CLK rise time
SDRAM CLK fall time
SDRAM Buffer LH prop delay
SDRAM Buffer HL prop delay
SDRAM Buffer Enable delay
SDRAM Buffer Disable delay
Measured at 1.5V
SDRAM Output to Output Skew
66 MHz
Min. Max.
15.0
15.5
5.6
5.3
1.5
4.0
1.5
4.0
1.0
5.0
1.0
5.0
1.0
8.0
1.0
8.0
45
55
250
100 MHz
Min. Max.
10.0
10.5
3.3
3.1
1.5
4.0
1.5
4.0
1.0
5.0
1.0
5.0
1.0
8.0
1.0
8.0
45
55
250
133.3 MHz
Min. Max.
7.5
8.0
2.2
2.0
1.4
4.0
1.4
4.0
1.0
5.0
1.0
5.0
1.0
8.0
1.0
8.0
45
45
250
Units
ns
V/ns
ns
%
ps
08-0298
4
PS8317F 11/13/08
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