PI7C7100CNA 查看數據表（PDF） - Pericom Semiconductor Corporation

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PI7C7100CNA

3-Port PCI Bridge

Pericom Semiconductor Corporation 

ADVANCE INFORMATION

PI7C7100

3-Port PCI Bridge 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566

3.2.3 Clock Signals

Name

Pin #

Type

P_CLK

V6

PI

S_CLKOUT T3, T1, P3, PTS

[15:0]

N3,M4, L3, L2,

J1,A11, C12,

A13, B14,

B15, C16,

A18, A19

Description

Primary Clock Input. Provides timing for all transaction on primary interface.

Secondary Clock Output. Provides secondary clocks phase synchronous with

the P_CLK.

3.2.4 Miscellaneous Signals

Name

Pin # Type

BYPASS

Y4

–

PLL_TM

Y3

–

S_CLKIN

V5

PI

SCAN_TM#

V4

CI

SCAN_EN

U5

CIU

CMPO1

Reserved

U6

–

R4

Description

Reserved for Future Use. Must be tied HIGH.

Reserved for Future Use. Must be tied LOW.

Secondary Test Clock Input. It should be tied to LOW in normal mode. It also

may be a secondary clock input for the secondary buses if both SCAN_TM# and

SCAN_EN are connected to logic "1".

Full-scan Test Mode enable (Active LOW). When SCAN_TM# is active, the

twelve scan chains will be enabled. The scan clock is P_CLK. The scan inputs and

outputs are as follows:

S1_REQ[7], S1_REQ[6], S1_REQ[5], S1_REQ[4], S1_REQ[3], S1_REQ[2],

S2_REQ[7], S2_REQ[6], S2_REQ[5], S2_REQ[4], S2_REQ[3], S2_REQ[2] and

S1_GNT[7], S1_GNT[6], S1_GNT[5], S1_GNT[4], S1_GNT[3], S1_GNT[2],

S2_GNT[7], S2_GNT[6], S2_GNT[5], S2_GNT[4], S2_GNT[3], S2_GNT[2]

respectively

Full-scan Enable Control. When SCAN_EN is LOW, full-scan is in shift operation

if SCAN_TM# is active. When SCAN_EN is HIGH, full-scan is in parallel operation

if SCAN_TM# is active. SCAN_EN should be tied LOW in normal mode. If

SCAN_TM# and SCAN_EN are connected to logic "1", S_CLKIN is the clock

source for the internal secondary clock. If SCAN_TM# is connected to logic "1" and

SCAN_EN is connected to logic "0", P_CLK is the clock source for the internal

secondary clock.

Note: During power-up, SCAN_EN is the reset signal for the on-chip PLL.

Reserved for Future Use.

Reserved

3.2.5 JTAG Boundary Scan Signals

Name Pin # Type Description

TCK

V2 CIU Test Clock. Used to clock state information and data into and out of the PI7C7100 during

boundary scan.

TMS

W1 CIU Test Mode Select. Used to control the state of the Test Access Port controller.

TDO

V3

CTO Test Data Output. When SCANEN is HIGH it is used (in conjunction with TCK) to shift data

out of the Test Access Port (TAP) in a serial bit stream.

TDI

W2 CIU Test Data Input. When SCANEN is HIGH it is used (in conjunction with TCK) to shift data

and instructions into the Test Access Port (TAP) a serial bit stream.

TRST# U3

CIU Test Reset. Active LOW signal to reset the Test Access Port (TAP) controller into an

initialized state.

8

09/18/00 Rev 1.1

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