SL2305SI-1 查看數據表（PDF） - Silicon Laboratories

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SL2305SI-1

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)

Silicon Laboratories 

Pin Configuration

CLKIN 1

CLK2 2

CLK1 3

GND 4

8 CLKOUT

7 CLK4

6 VDD

5 CLK3

8-Pin SOIC or TSSOP

SL2305

Pin Description

Pin

Pin Name

Number

1

CLKIN

2

CLK2

3

CLK1

4

GND

5

CLK3

6

VDD

7

CLK4

8

CLKOUT

Pin Type Pin Description

Input

Output

Output

Power

Output

Power

Output

Output

Reference Frequency Clock Input. Weak pull-down (250kΩ).

Buffered Clock Output Weak pull-down (250kΩ).

Buffered Clock Output. Weak pull-down (250kΩ).

Power Ground.

Buffered Clock Output. Weak pull-down (250kΩ).

3.3V Power Supply.

Buffered Clock Output. Weak pull-down (250kΩ).

Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull-

down (250kΩ).

Rev 2.1, October 22, 2007

Page 2 of 11

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