GS881Z18BD 查看數據表（PDF） - Giga Semiconductor

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GS881Z18BD

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS881Z18B(T/D)/GS881Z32B(T/D)/GS881Z36B(T/D)

Flow Through Mode Data I/O State Diagram

BW

R

High Z

(Data In)

D

WR

High Z

B

D

RB

Data Out

W (Q Valid)

D

Key

Input Command Code

ƒ Transition

Current State (n)

Next State (n+1)

n

n+1

Clock (CK)

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

n+2

n+3

Command

ƒ

ƒ

ƒ

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram

Rev: 1.04 10/2004

15/39

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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