APW7068KE-TRG 查看數據表（PDF） - Anpec Electronics

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APW7068KE-TRG

Synchronous Buck PWM and Linear Controller with 0.8V Reference Out Voltage

Anpec Electronics 

APW7068

Pin Description

SOP-14

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PIN

NO.

SSOP-16 QFN4x4-16

NAME

FUNCTION

This pin provides the bootstrap voltage to the upper gate driver for driving the

1

15

BOOT

N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal

diode, and the power supply voltage VCC12, generates the bootstrap voltage

for the upper gate diver (UGATE).

This pin provides shutdown function. When pulling low the FS_DIS pin near

2

16

FS_DIS

GND will shutdown both regulators; almost any NFET or other pull-down

device (< 1k. impedance) should work. Upon release of the FS_DIS pin, it will

enable both outputs back into regulation.

3

1

COMP

This pin is the output of PWM error amplifier. It is used to set the

compensation components.

This pin is the inverting input of the PWM error amplifier. It is used to set the

4

2

FB

output voltage and the compensation components. This pin is also monitored

for under-voltage protection, when the FB voltage is under 50% of reference

voltage (0.4V), both outputs will be shutdowned immediately.

This pin drives the gate of an external N-channel MOSFET for linear regulator.

5

3

DRIVE It is also used to set the compensation for some specific applications, for

example, with low values of output capacitance and ESR.

This pin is the inverting input of the linear regulator error amplifier. It is used to

6

4

FBL

set the output voltage. This pin is also monitored for under-voltage protection,

when the FBL voltage is under 50% of reference voltage

(0.4V), both outputs will be shutdown immediately.

7,8

5,6

GND

This pin is the signal ground pin. Connect the GND pin to a good ground

plane.

Power supply input pin. Connect a nominal 12V power supply to this pin. The

9,10

7,8

VCC12

power-on reset function monitors the input voltage at this pin. It is

recommended that a decoupling capacitor (1 to 10µF) be connected to GND

for noise decoupling.

This pin provides a buffed voltage, which is from internal reference voltage. It

11

9

REF_OUT

is recommended

When VOCSET

that a 1mF capacitor is connected to ground

is above 1V, the REF_OUT buffer will be

for stability.

closed, the

VREF_OUT is 0V.

Connect a resistor (ROCSET) from this pin to GND, an internal 40mA current

source will flow through this resistor and create a voltage drop. When VCC12

reaches the POR rising threshold voltage, the voltage drop of ROCSET will be

memoried and compared with the voltage across the lower MOSFET. The

threshold of the over current limit is therefore given by:

12

10

OCSET

ILIMIT

=

IOCSET × ROCSET

RDS(ON)(LOW − Side)

The APW7068 has a internal OCP voltage source, and the value is around

0.25V. When the ROCSET x IOCSET is bigger than 0.25V or the OCSET PIN

is floating (no ROCSET resistor), the over current threshold will be the internal

default value 0.25V.

13

11

LGATE This pin is the gate driver for the lower MOSFET of PWM output.

14

12

PGND

This pin is the power ground pin for the lower gate driver. It should be tied to

GND pin on the board.

This pin is the return path for the upper gate driver. Connect this pin to the

15

13

PHASE

upper MOSFET source, and connect a capacitor to BOOT for the bootstrap

voltage. This pin is also used to monitor the voltage drop across the lower

MOSFET for over-current protection.

16

14

UGATE This pin is the gate driver for the upper MOSFET of PWM output.

Copyright © ANPEC Electronics Corp.

11

Rev. A.6 - Aug., 2009

www.anpec.com.tw

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