74LVC1G38 查看數據表（PDF） - Nexperia B.V. All rights reserved
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74LVC1G38 Datasheet PDF : 19 Pages
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Nexperia
74LVC1G38
2-input NAND gate; open drain
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74LVC1G38GW 40 C to +125 C TSSOP5
74LVC1G38GV
74LVC1G38GM
40 C to +125 C
40 C to +125 C
SC-74A
XSON6
74LVC1G38GF
40 C to +125 C XSON6
74LVC1G38GN 40 C to +125 C XSON6
74LVC1G38GS 40 C to +125 C XSON6
74LVC1G38GX 40 C to +125 C X2SON5
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic surface-mounted package; 5 leads
SOT753
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 1 0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9 1.0 0.35 mm
SOT1115
extremely thin small outline package; no leads;
6 terminals; body 1.0 1.0 0.35 mm
SOT1202
X2SON5: plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 0.8 0.35 mm
SOT1226
4. Marking
Table 2. Marking
Type number
74LVC1G38GW
74LVC1G38GV
74LVC1G38GM
74LVC1G38GF
74LVC1G38GN
74LVC1G38GS
74LVC1G38GX
Marking code[1]
YB
YB
YB
YB
YB
YB
YB
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
$
%
<
DDE
Fig 1. Logic symbol
DDE
Fig 2. IEC logic symbol
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$
%
*1'
DDE
Fig 3. Logic diagram
74LVC1G38
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 7 December 2016
© Nexperia B.V. 2017. All rights reserved
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