AAT3236(2001) 查看數據表（PDF） - Advanced Analogic Technologies
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AAT3236 Datasheet PDF : 16 Pages
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AAT3236
300mA CMOS High Performance LDO
The problem with the layout in Figure 18 is the
bypass capacitor and output capacitor share the
same ground path to the LDO regulator ground pin
along with the high current return path from the load
back to the power supply. The bypass capacitor
node is connected directly to the LDO regulator
internal reference, making this node very sensitive
to noise or ripple. The internal reference output is
fed into the error amplifier, thus any noise or ripple
from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This
effect can increase noise seen on the LDO regulator
output as well as reduce the maximum possible
power supply ripple rejection. There is PCB trace
impedance between the bypass capacitor connec-
tion to ground and the LDO regulator ground con-
nection. When the high load current returns through
this path, a small ripple voltage is created, feeding
into the CBYP loop.
Figure 19 shows the preferred method for the
bypass and output capacitor connections. For low
output noise and highest possible power supply
ripple rejection performance, it is critical to connect
the bypass and output capacitor directly to the LDO
regulator ground pin. This method will eliminate
any load noise or ripple current feedback through
the LDO regulator.
Evaluation Board Layout
The AAT3236 evaluation layout follows the recom-
mend printed circuit board layout procedures and
can be used as an example for good application
layouts.
Note: Board layout shown is not to scale.
IIN
VIN
DC INPUT
ILOAD
VIN
LDO VOUT
Regulator
EN
BYP
GND
CIN
IRIPPLE
IGND
IBYP only
CBYP
GND
RTRACE
RTRACE
ILOAD return + noise and ripple
Figure 19: Recommended LDO Regulator Layout
RTRACE
COUT
RTRACE
RLOAD
Figure 20: Evaluation board
component side layout
Figure 21: Evaluation board
solder side layout
Figure 22: Evaluation board
top side silk screen layout /
assembly drawing
3236.2001.11.0.9
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