MX29LV161DB 查看數據表（PDF） - Macronix International

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MX29LV161DB

16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY

Macronix International 

MX29LV161D T/B

BLOCK DIAGRAM DESCRIPTION

The block diagram on Page 10 illustrates a simplified architecture of MX29LV161D T/B. Each block in the block

diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the

memory array.

The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET# and WP#/ACC. It creates

internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER"

to latch the external address pins A0-AM(A19). The internal addresses are output from this block to the main ar-

ray and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", and "FLASH ARRAY". The X-

DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash ar-

ray. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through

the y-pass gates. Sense amplifiers are used to read out the contents of the flash memory, while the "PGM DATA

HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls

the input and output on the Q0-Q15 pads. During read operation, the I/O buffer receives data from sense ampli-

fiers and drives the output pads accordingly. In the last cycle of program command, the I/O buffer transmits the

data on Q0-Q15 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to se-

lectively program the bits in a word according to the user input pattern.

The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary

high voltage to the "X-DECODER", "FLASH ARRAY", and "PGM DATA HV" block. The logic control module

comprises of the "WRITE STATE MACHINE(WSM)", "STATE REGISTER", "COMMAND DATA DECODER", and

"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15 is

latched in the command data latch and is decoded by the command data decoder. The state register receives

the command and records the current state of the device. The WSM implements the internal algorithms for pro-

gram or erase according to the current command state by controlling each block in the block diagram.

P/N:PM1359

REV. 1.0, JUN. 03, 2010

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