82C836 查看數據表（PDF） - Unspecified

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82C836

Single-Chip 386sx AT

Unspecified 

Pin Assignments

Signal Descriptions s

Table 2-3. Numeric Coprocessor Interface Signals

Pin

Type

133

Output

127

Input

128

Input

Name

-BUSY

-NPBUSY

-NPERR

Description

Numeric coprocessor busy status output to the

80386sx. This signal normally echoes the state of

-NPBUSY from the 80387sx. During coprocessor

error conditions, it is held low. Also, it is pulsed

repetitively by the 82C836 when no coprocessor is

present.

Busy status from 80387sx. This signal indicates the

80387sx is currently executing a command.

Error signal from the coprocessor.

Table 2-4. Memory Interface Signals

Pin

108-117

107-104

Type

Output

Output

Name

MA0-MA9

-RAS<0:3>,

(MA10)

101

Output

-CASH

100

Output

-CASL

119

Bidirectional

PARH

118

Bidirectional

PARL

103

Output

-MWE

38

Output

-ROMCS

Description

Multiplexed DRAM address bits MA 0 to 9 are

outputs to the DRAMs

Row Address Strobes 0 to 3 are active-low strobes

used as RAS controls for the banks of DRAM. Each

bank is 18 bits wide (including 2 bits for parity).

Each byte is addressed with an even or odd CAS

signal. -RAS<0:3>, perform different functions in

an encoded RAS mode. When using a 4MB DRAM

configuration, -RAS3 becomes MA10. For further

details, refer to Section 5, System Interface, subsection

titled DRAM Interface.

Column Address Strobe High is an active-low output

to all high (odd) byte DRAMs.

Column Address Strobe Low is an active-low output

to all low (even) byte DRAMs.

Parity High is the parity bit from the high-order bytes

of the DRAMs.

Parity Low is the parity bit from the low-order bytes

of the DRAMs.

Memory Write Enable is an active-low output

connected to all DRAMs. -MWE is normally low, but

is high for read cycle. This signal can also be used

directly to control the direction of the transceivers (if

present) that buffer the DRAM data to or from the

CPU local data bus.

ROM Chip Select is an active-low output to the

EPROM(s). -ROMCS becomes active for the

progammed address range.

Chips and Technologies, Inc.

PRELIMINARY

Revision 3.0 2-5

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