82C836A 查看數據表（PDF） - Unspecified
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82C836A Datasheet PDF : 205 Pages
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Pin Assignments
Signal Descriptions s
Table 2-5. I/O Channel Interface Signals (continued)
Pin
41
40
83
82
42
54-50
49
84-86
88-87
90
48
46
44
92
94
Type
Input
Name
IOCHRDY
Input
-0WS (-LBA)
Bidirectional
-IOCS16
Bidirectional
-MEMCS16
Input
Input
Input
Input
Input
-IOCHCK
IRQ0<3:7>
IRQ09
IRQ<10:12>
IRQ<14:15>
Input
Input
Input
Input
Input
Input
DRQ0/DSELB
DRQ1/DSELA
DRQ2/DRQA
DRQ3/DRQB
DRQ5/-CAS3H
DRQ6/-CAS2H
Description
I/O Channel Ready is used by I/O channel or
XD-bus devices to lengthen their R/W cycles.
Normally, IOCHRDY is high; it is pulled low to
extend the cycle time. This input should be driven
by an open collector driver.
Zero Wait-State is an active-low input from the I/O
channel. This signal allows the present bus cycle to
terminate without inserting any additional wait-states
-0WS should be driven with an open collector or a
tri-state driver. For external cache support, this
signal can also be programmed to act as a Local Bus
Access (-LBA) input as well as the AT bus -0WS
input.
I/O 16-bit Chip Select is an active-low signal.
-IOCS16 is an input from the I/O channel and
XD-bus peripherals, indicating that the accessed
resource can support 16-bit data transfers. -IOCS16
is an output for I/O accesses to the EMS I/O ports.
-IOCS16 should be driven with an open collector or
tri-state driver.
Memory 16-bit Chip Select is an active-low signal.
-MEMCS16 is an input from the I/O channel and
XD-bus peripherals, indicating that the accessed
resource can support 16-bit data transfers.
-MEMCS16 is an output for CPU or Master accesses
to on-board DRAM or to 16-bit on-board ROM.
I/O Channel Check is an active-low signal from the
I/O channel used to trigger an NMI in the processor
in the event of an unrecoverable I/O channel error.
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Interrupt Requests 3-7, 9, 10-12, 14-15 are
asynchronous inputs to the 82C836 interrupt
controllers. These requests are prioritized with
IRQ03 having the highest priority and IRQ15 the
lowest. The request line is held active until
acknowledged by the processor with an interrupt
acknowledge cycle.
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Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 2-7
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