A625308A_06 查看數據表（PDF） - AMIC Technology

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A625308A_06

32K X 8 BIT CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Write Cycle 2 (6)

(Chip Enable Controlled)

Address

CE

WE

DIN

DOUT

(4)

tAS1

tWC

tAW

tCW5

tWP2

tDW

tWHZ7

tWR3

tDH

A625308A Series

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE and a low WE .

3. tWR is measured form the earliest of CE or WE going high to the end of the Write cycle.

4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs

remain in a high impedance state.

5. tCW is measured from the later of CE going low to the end of Write.

6. OE level is high or low.

7. Transition is measured ±500mV from steady. This parameter is sampled and not 100% tested.

(September, 2006, Version 1.3)

8

AMIC Technology, Corp.

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