ISL55100BIRZ-T 查看數據表（PDF） - Renesas Electronics
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ISL55100BIRZ-T Datasheet PDF : 14 Pages
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ISL55100B
Electrical Specifications Test Conditions: VCC = 12V, VEE = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, VEXT = VEE and
LOWSWING = VCC, +25°C; Unless Otherwise specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS VEXT = VEE + 5.5V, EXTERNAL LOGIC POWER OPTION USED. (Note 11)
Positive Supply Current
ICC
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE
-
35
50
mA
+ 5.5V, outputs unloaded
Negative Supply Current
IEE
VCC = VH = 12V, VEE = VL = -3V, VEXT = VEE
-50
-35
-
mA
+ 5.5V, outputs unloaded
VEXT Supply Current
IEXT VCC = VH = 12, VEE = VL = -3V, VEXT = VEE +
-
25
40
mA
5.5V, outputs unloaded
NOTES:
6. Lab characterization, room temp, Timing Parameters Matched Stimulus/Loads, Channel-to-Channel Skew < 500ps, 1ns Max by design.
7. Measured across 100pF/1k lump sum load + 15pF PCB/Scope Probe. Cap and Resistor Surface Mount/Stacked ~0.5” from Pin.
8. To Enable LOWSWING, connect LOWSWING to VEE and keep VH < VEE + 5. To disable LOWSWING, connect it to VCC.
9. When VEXT is connected to VEE (External Device Power not used) then the Minimum VCC - VEE is 12V. When VEXT is connected to an external 5.5V
supply, then the minimum VCC - VEE voltage is 9V. Recommended VEXT = 5.5V as referenced to VEE.
10. ICC and IEE values are based on static conditions and will increase with pattern rates. ICC and IEE reach 400mA to 500mA at maximum data rates
(provided sufficient device cooling is employed). These currents can be reduced by 1) Reducing the VCC - VEE operating voltage 2) Utilizing the VEXT
option.
11. When using VEXT = 5.5V, current requirements of the VEXT input can approach 100mA at maximum pattern rates.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.When using VEXT = 5.5V, current requirements of the VEXT input can approach 100mA at maximum pattern rates.
13. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 9 for more
information.
Test Circuits and Waveforms
VH
VL
DATA+
DATA-
DRV EN+
DRV EN-
DOUT
(Note 7)
100pF
VO
1kΩ
FIGURE 1. DRIVER SWITCHING TEST CIRCUIT
DATA-
DATA+
tPDLH
DATA = 1
VO
50%
tR
DATA = 0
400mV
0V
tPDHL
50%
VOH (VH)
VOL (VL)
tF
FIGURE 2. DRIVER PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
FN6229 Rev 2.00
December 4, 2014
Page 6 of 14
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