ISL83483IB 查看數據表（PDF） - Intersil
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产品描述 (功能)
比赛名单
ISL83483IB Datasheet PDF : 17 Pages
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ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = 25oC,
Note 2 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(oC) MIN TYP MAX UNITS
Driver Disable from Output Low
(Except ISL83488)
tLZ
RL = 110Ω, CL = 50pF, SW = VCC (Figure 3)
25
-
Full
-
70
80
ns
-
110 ns
Driver Enable from Shutdown to tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes 7, 8)
Full
-
Output High (Except ISL83488)
450 2000 ns
Driver Enable from Shutdown to
Output Low (Except ISL83488)
tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 3),
(Notes 7, 8)
Full
-
126 2000 ns
RECEIVER SWITCHING CHARACTERISTICS (All Versions)
Receiver Input to Output Delay
Receiver Skew | tPLH - tPHL |
tPLH, tPHL (Figure 4)
tSKD (Figure 4)
Full 25
45
90
ns
25
-
2
10
ns
Full
-
2
12
ns
Receiver Enable to Output High
(Except ISL83488 and ISL83490)
tZH
RL = 1kΩ, CL = 15pF, SW = GND (Figure 5),
(Note 6)
Full
-
11
50
ns
Receiver Enable to Output Low
(Except ISL83488 and ISL83490)
tZL
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5),
(Note 6)
Full
-
11
50
ns
Receiver Disable from Output High
(Except ISL83488 and ISL83490)
tHZ
RL = 1kΩ, CL = 15pF, SW = GND (Figure 5)
Full
-
7
45
ns
Receiver Disable from Output Low
(Except ISL83488 and ISL83490)
tLZ
RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5)
Full
-
7
45
ns
Time to Shutdown
(Except ISL83488 and ISL83490)
tSHDN (Note 7)
Full 80
190 300
ns
Receiver Enable from Shutdown to tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 5),
Output High
(Notes 7, 9)
(Except ISL83488 and ISL83490)
Full
-
240 600 ns
Receiver Enable from Shutdown to tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5),
Output Low
(Notes 7, 9)
(Except ISL83488 and ISL83490)
Full
-
240 600 ns
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL83483, ISL83485, ISL83491, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL83483, ISL83485, ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device from
entering SHDN.
7. The ISL83483, ISL83485, ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, the
parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are guaranteed to have entered shutdown.
See “Low-Power Shutdown Mode” section.
8. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN.
9. Set the RE signal high time >300ns to ensure that the device enters SHDN.
7
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