ISL8002 查看數據表（PDF） - Renesas Electronics
零件编号
产品描述 (功能)
比赛名单
ISL8002 Datasheet PDF : 23 Pages
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ISL8002, ISL8002A, ISL80019, ISL80019A
Pin Configuration
ISL8002, ISL8002A, ISL80019, ISL80019A
(8 LD 2x2 TDFN)
TOP VIEW
VIN 1
EN 2
MODE 3
PG 4
THERMAL
PAD
(GPANDD)
PIN 9
8 PHASE
7 PGND
6 FB
5 COMP
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
PIN NAME
PIN DESCRIPTION
VIN
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
EN
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
MODE
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM
mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left
floating, however, it is not recommended to leave this pin floating.
PG
Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation
limits. There is an internal 5MΩ internal pull-up resistor on this pin.
COMP
COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is
connected with a series resistor and capacitor to GND, compensation is external. See “Loop Compensation Design” on
page 20 for more detail.
FB
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
PGND
Power and analog ground connections. Connect directly to the board GROUND plane.
PHASE
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an
100Ω resistor when the device is disabled. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as-well-as a thermal
(T-PAD) path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad.
FN7888 Rev 4.00
July 31, 2014
Page 4 of 23
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