ICM7555 查看數據表（PDF） - Renesas Electronics

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ICM7555

General Purpose Timers

Renesas Electronics 

ICM7555, ICM7556

1

2

OUTPUT

3

VDD

4

VDD

RA

8

7

6

5

RB

C

OPTIONAL

CAPACITOR

FIGURE 5. ALTERNATE ASTABLE CONFIGURATION

OUTPUT DRIVE CAPABILITY

The output driver consists of a CMOS inverter capable of

driving most logic families including CMOS and TTL. As such, if

driving CMOS, the output swing at all supply voltages will equal

the supply voltage. At a supply voltage of 4.5V or more, the

ICM7555 and ICM7556 will drive at least two standard TTL

loads.

ASTABLE OPERATION

The circuit can be connected to trigger itself and free run as a

multivibrator, see Figure 4. The output swings from rail-to-rail,

and is a true 50% duty cycle square wave. Trip points and

output swings are symmetrical. Less than a 1% frequency

variation is observed over a voltage range of +5V to +15V.

f = 1----.--4--1---R----C---

(EQ. 1)

The timer can also be connected as shown in Figure 5. In this

circuit, the frequency is as shown by Equation 2:

f = 1.44 ⁄ (RA + 2RB)C

(EQ. 2)

The duty cycle is controlled by the values of RA and RB, by

Equation 3:

D = (RA + RB) ⁄ (RA + 2RB)

(EQ. 3)

MONOSTABLE OPERATION

In this mode of operation, the timer functions as a one-shot (see

Figure 6). Initially the external capacitor (C) is held discharged by

a transistor inside the timer. Upon application of a negative

Trigger pulse to pin 2, the internal flip-flop is set, which releases

the short-circuit across the external capacitor and drives the

Output high. The voltage across the capacitor now increases

exponentially with a

across the capacitor

time constant t

equals 2/3 V+,

= RAC. When the voltage

the comparator resets the

flip-flop, which in turn discharges the capacitor rapidly and also

drives the OUTPUT to its low state. Trigger must return to a high

state before the OUTPUT can return to a low state.

tOUTPUT = -ln (1/3) RAC = 1.1RAC

VDD

RA

1

8

TRIGGER

OUTPUT

DISCHARGE

2

7

ICM7555

THRESHOLD

3

6

CONTROL

RESET

4

5 VOLTAGE

VDD ≤18V

OPTIONAL

CAPACITOR

C

FIGURE 6. MONOSTABLE OPERATION

CONTROL VOLTAGE

The Control Voltage terminal permits the two trip voltages for

the Threshold and Trigger internal comparators to be

controlled. This provides the possibility of oscillation frequency

modulation in the astable mode or even inhibition of

oscillation, depending on the applied voltage. In the

monostable mode, delay times can be changed by varying the

applied voltage to the Control Voltage pin.

RESET

The Reset terminal is designed to have essentially the same

trip voltage as the standard bipolar 555/556, i.e., 0.6V to 0.7V.

At all supply voltages it represents an extremely high input

impedance. The mode of operation of the Reset function is,

however, much improved over the standard bipolar

SE/NE 555/556 in that it controls only the internal flip-flop,

which in turn controls simultaneously the state of the Output

and Discharge pins. This avoids the multiple threshold

problems sometimes encountered with slow falling edges in

the bipolar devices.

FN2867 Rev.10.01

Mar 5, 2020

Page 6 of 13

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