CY7C1412KV18(2011) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1412KV18
(Rev.:2011)

36-Mbit QDR® II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

CY7C1410KV18, CY7C1425KV18

CY7C1412KV18, CY7C1414KV18

Logic Block Diagram (CY7C1412KV18)

D[17:0]

18

A(19:0) 20

Address

Register

Write

Reg

Write

Reg

K

K

DOFF

VREF

WPS

BWS[1:0]

CLK

Gen.

Control

Logic

Read Data Reg.

36

18

18

Address

Register

20

A(19:0)

Control

Logic

RPS

C

C

Reg.

Reg. 18

Reg.

18

18

CQ

CQ

Q[17:0]

Logic Block Diagram (CY7C1414KV18)

D[35:0]

36

A(18:0) 19

Address

Register

K

K

DOFF

VREF

WPS

BWS[3:0]

CLK

Gen.

Control

Logic

Write

Reg

Write

Reg

Address

Register

19

A(18:0)

Read Data Reg.

72

36

36

Control

Logic

RPS

C

C

Reg.

Reg. 36

Reg.

36

36

CQ

CQ

Q[35:0]

Document Number: 001-57825 Rev. *C

Page 3 of 30

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