CY7C1462AV33 查看數據表（PDF） - Cypress Semiconductor

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CY7C1462AV33

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1460AV33

CY7C1462AV33

CY7C1464AV33

Logic Block Diagram-CY7C1462AV33 (2M x 18)

A0, A1, A

MODE

CLK

C

CEN

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

C

WRITE ADDRESS

REGISTER 2

ADV/LD

BWa

BWb

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

O

U

T

S

E

N

P

U

T

WRITE

DRIVERS

S

MEMORY

E

ARRAY

A

M

P

S

R

E

G

I

S

T

E

R

S

E

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

G

E

INPUT

REGISTER 1 E

INPUT

REGISTER 0 E

DQs

DQPa

DQPb

OE

CE1

CE2

CE3

ZZ

READ LOGIC

Sleep

Control

Logic Block Diagram-CY7C1464AV33 (512K x 72)

A0, A1, A

MODE

CLK

C

CEN

ADDRESS

REGISTER 0

WRITE ADDRESS

REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

C

WRITE ADDRESS

REGISTER 2

ADV/LD

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

WE

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

O

U

T

S

E

N

P

U

T

WRITE

DRIVERS

S

MEMORY

E

ARRAY

A

M

P

S

R

E

G

I

S

T

E

R

S

E

O

U

T

D

P

A

U

T

T

A

B

S

U

T

F

E

F

E

E

R

R

I

S

N

G

E

INPUT

REGISTER 1 E

INPUT

REGISTER 0 E

DQs

DQPa

DQPb

DQPc

DQPd

DQPe

DQPf

DQPg

DQPh

OE

CE1

CE2

CE3

ZZ

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby

Current

READ LOGIC

Sleep

Control

250 MHz

2.6

475

120

200 MHz

3.2

425

120

167 MHz

Unit

3.4

ns

375

mA

120

mA

Document #: 38-05353 Rev. *D

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