CY7C1471V33(2004) 查看數據表（PDF） - Cypress Semiconductor

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CY7C1471V33
(Rev.:2004)

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1471V33

CY7C1473V33

CY7C1475V33

Truth Table (continued)[2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK

DQ

Write Cycle (Continue Burst) Next X X X L

H

X

L

X

L L->H Data In (D)

NOP/Write Abort (Begin Burst) None L H L L

L

L

HX

L L->H Tri-State

Write Abort (Continue Burst) Next X X X L

H

X

HX

L L->H Tri-State

Ignore Clock Edge (Stall) Current X X X L

X

X

X

X

H L->H

-

Sleep Mode

None X X X H

X

X

X

X

X X Tri-State

Truth Table for Read/Write[2, 3, 9]

Read

Function (CY7C1471V33)

Write No bytes written

Write Byte A – (DQA and DQPA)

Write Byte B – (DQB and DQPB)

Write Byte C – (DQC and DQPC)

Write Byte D – (DQD and DQPD)

Write All Bytes

Truth Table for Read/Write[2, 3, 9]

WE

BWA

BWB

BWC

BWD

H

X

X

X

X

L

H

H

H

H

L

L

H

H

H

L

H

L

H

H

L

H

H

L

H

L

H

H

H

L

L

L

L

L

L

Read

Function (CY7C1473V33)

WE

BWB

BWA

H

X

X

Write – No Bytes Written

L

H

H

Write Byte a – (DQa and DQPa)

Write Byte b – (DQb and DQPb)

Write Both Bytes

Truth Table for Read/Write[2, 3, 9]

L

H

L

L

L

H

L

L

L

Read

Function (CY7C1475V33)

WE

BWx

H

X

Write – No Bytes Written

L

H

Write Byte X − (DQx and DQPx)

Write All Bytes

L

L

L

All BW = L

Note:

9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.

Document #: 38-05288 Rev. *E

Page 11 of 29

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