PORT BLOCK DIAGRAMS (CONTINUED)
External interrupt
EXF0
Key-on wakeup
input
Register A
One-sided edge
detection circuit
K02 Rising
0
1
Falling
IAG instruction
A0
OGA instruction
DQ
T
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Pull-up transistor
PU00
(Note 1)
G0/INT
K01
Key-on wakeup
input
Register A
IAG instruction
Timer 1 underflow
signal output
A1
DQ
OGA instruction T
1/2
1
0
V13
Pull-up transistor
PU00
(Note 1)
G1/TOUT
Key-on wakeup
input
Register A
K01
IAG instruction
(Note 2) Ak
OGA instruction
DQ
T
Pull-up transistor
PU00
(Note 1)
G2, G3
Notes 1:
This symbol represents
a parasitic diode.
Applied potential to ports G0–G3
must be VDD or less.
2: k represents 2 or 3.
10