42552 查看數據表（PDF） - Peregrine Semiconductor Corp.
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42552 Datasheet PDF : 9 Pages
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PE42552
Product Specification
Low Frequency Power Handling: ZL = 50Ω
Figure 4 provides guidelines of how to adjust the Vdd
and input Power to the 42552 device. The upper limit
curve represents the maximum Input Power vs Vdd
recommended for this part.
Figure 4. Maximum Operating Power Limit
vs. Vdd and Input Power @ 9 KHz
Upper Power Limit
8
6
4
2
0
-2
-4
-6
-8
-10
-12
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Vdd (V)
To allow for sustained operation under any load VSWR condition,
max power should be kept 6dB lower than max power in 50 Ohm.
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Figure 5 shows how the power limit in Figure 4 will
increase with frequency. As the frequency increases,
the contours and Maximum Power Limit Curve will
increase with the increase in power handling shown on
the curve.
Figure 5. Operating Power Offset vs.
Frequency (Normalized to 9kHz)
30
25
20
15
10
5
0
1
10
100
1000
Freq (kHz)
Power Handling Examples
Example 1: Maximum power handling at 100kHz, Z=50
ohms, VSWR 1:1, and Vdd=3V
• The power handling offset for 100kHz from Fig. 5 is
10dB
• The max power handling at Vdd = 3V is 5.5dB from
Fig. 4
• Derate power under mismatch conditions
• Total maximum power handling for this example is
10dB + 5.5dB = 15.5dBm
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
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