LC863428A 查看數據表（PDF） - SANYO -> Panasonic

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LC863428A

8-Bit Single-Chip Microcontroller

SANYO -> Panasonic 

LC863432A/28A/24A/20A/16A

(6) Ports

- Input / Output Ports

: 4 ports (23 terminals)

Data direction programmable in nibble units

: 1 port (8 terminals)

(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)

Data direction programmable for each bit individually : 3 ports (15 terminals)

(7) AD converter

- 4 channels × 6-bit AD converters

(8) Serial interfaces

- IIC-bus compliant serial interface (Multi-master type)

Consists of a single built-in circuit with two I/O channels.

internally.

The two data lines and two clock lines can be connected

(9) PWM output

- 3 channels × 7-bit PWM

(10) Timer

- Timer 0 : 16-bit timer/counter

With 2-bit prescaler + 8-bit programmable prescaler

Mode 0 : Two 8-bit timers with a programmable prescaler

Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter

Mode 2 : 16-bit timer with a programmable prescaler

Mode 3 : 16-bit counter

The resolution of timer is 1 tCYC.

- Base timer

Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)

Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer

clock)

Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler

output of Timer 0

(11) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)

- Noise rejection function

- Polarity switching

(12) Watchdog timer

External RC circuit is required

Interrupt or system reset is activated when the timer overflows

(13) ROM correction function

Max 128 bytes / 2 addresses

(14) Interrupts

- 11 sources 8 vectored interrupts

1. External Interrupt INT0

2. External Interrupt INT1

3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)

4. External Interrupt INT3, base timer

5. Timer/counter T0H (Upper 8 bits)

6. Data slicer

7. Vertical synchronous signal interrupt ( VS ), horizontal line ( HS )

8. IIC

- Interrupt priority control

Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high

priority can be assigned to the interrupts from 3 to 8 listed above. For the external interrupt INT0 and INT1, low or

highest priority can be set.

No.6846-3/19

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