datasheetbank_Logo
数据手册搜索引擎和 Datasheet免费下载 PDF

LC86E4564 查看數據表(PDF) - SANYO -> Panasonic

零件编号
产品描述 (功能)
比赛名单
LC86E4564
SANYO
SANYO -> Panasonic SANYO
LC86E4564 Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC86E4564
2. Recommended Operating Range at Ta = +10°C to +40°C, VSS = 0 V
Parameter
Operating
supply
voltage range
Hold voltage
Input high
voltage
Input low
voltage
Operation
cycle time
Oscillation
frequency range
(Note 1)
Oscillation
stable time
period (Note 2)
Symbol
Pins
VDD
DVDD, AVDD
Conditions
0.98 µs tCYC
tCYC 1.02 µs
VDD [V]
Ratings
Unit
min typ max
4.5
5.5 V
VHD
VIH(1)
VIH(2)
VIH(3)
VIH(4)
VIH(5)
VIL(1)
VIL(2)
VIL(3)
VIL(4)
VIL(5)
tCYC(1)
tCYC(2)
FmCF
FmLC
FmRC
tmsCF
DVDD, AVDD
RAMs and the
registers hold data at
HOLD mode.
Port 0 (Schmitt)
Output disable
Port 1 (Schmitt)
P72, 73
HS, VS
Output disable
P70
port input / interrupt
P71
RES
(Schmitt)
Output N-channel
transistor OFF
P70
Output N-channel
Watchdog timer input transistor OFF
Port 9 DA0, 1
port input
Port 0 (Schmitt) Output disable
Port 1
P72, 73
HS, VS
Port 9
(Schmitt)
Output disable
P70
port input / interrupt
P71
RES
(Schmitt)
P70
Watchdog timer input
N-channel transistor
OFF
N-channel transistor
OFF
Port 9 DA0, 1
port input
OSD function
Except OSD function
CF1, CF2
LC1, LC2
CF1, CF2
12 MHz (ceramic
resonator oscillation)
Refer to Figure 1.
14.11 MHz
(LC oscillation)
Refer to Figure 2.
RC oscillation
12 MHz (ceramic
resonator oscillation)
Refer to Figure 3.
2.0
5.5
4.5 to 5.5 0.6VDD
VDD
4.5 to 5.5 0.75VDD
VDD
4.5 to 5.5 0.75VDD
VDD
4.5 to 5.5 VDD0.5
4.5 to 5.5 0.7VDD
4.5 to 5.5
VSS
4.5 to 5.5
VSS
VDD
VDD
0.2VDD
0.25VDD
4.5 to 5.5
VSS
0.25VDD
4.5 to 5.5
VSS
0.6VDD
4.5 to 5.5
VSS
0.3VDD
4.5 to 5.5
4.5 to 5.5
0.98 1
0.98
4.5 to 5.5 11.76
12
1.02 µs
30
12.24 MHz
4.5 to 5.5 14.11
4.5 to 5.5
4.5 to 5.5
0.4 0.8
0.02
3.0
0.2 ms
Note 1:
Note 2:
Refer to Table 1 and Table 2 for oscillation constant.
The oscillation stable time period refers to the time it takes to oscillate stably after the following conditions.
1. Applying the first supply voltage.
2. Release of the HOLD mode.
3. Release of the stopping of the main-clock oscillation.
No. 5584-10/19

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]