AD7676 查看數據表（PDF） - Analog Devices
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产品描述 (功能)
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AD7676 Datasheet PDF : 20 Pages
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AD7676
Pin No. Mnemonic
1
2
3, 6, 7,
40–42,
44–48
4
AGND
AVDD
NC
BYTESWAP
Type
P
P
DI
5
OB/2C
DI
8
SER/PAR
DI
9, 10 D[0:1]
DO
11, 12 D[2:3] or
DI/O
DIVSCLK[0:1]
13
D[4]
DI/O
or EXT/INT
14
D[5]
DI/O
or INVSYNC
15
D[6]
DI/O
or INVSCLK
16
D[7]
DI/O
or RDC/SDIN
17
OGND
P
18
OVDD
P
19
DVDD
P
20
DGND
P
PIN FUNCTION DESCRIPTIONS
Description
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
Parallel Mode Selection (8-Bit/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary. When LOW, the MSB is inverted resulting in a twos complement output from its internal
shift register.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected. When HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in
high impedance.
When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for
choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to
an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both Master and Slave Modes.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When
EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data is output
on SDOUT only when the conversion is complete.
Input/Output Interface, Digital Power Ground
Input/Output Interface, Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground
REV. B
–5–
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