UT62V25616MC-100LLI 查看數據表（PDF） - Utron Technology Inc
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UT62V25616MC-100LLI Datasheet PDF : 12 Pages
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Rev. 1.1
UTRON
UT62V25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
MAX
6
8
UNIT
pF
pF
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0V to 2.2V
5ns
1.2V
CL = 30pF, IOH/IOL = -0.5mA / 0.5mA
AC ELECTRICAL CHARACTERISTICS (VCC =2.3V~2.7V, TA = -40℃ to 85℃(I))
(1) READ CYCLE
PARAMETER
SYMBOL
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
LB , UB Access Time
LB , UB to High-Z Output
LB , UB to Low-Z Output
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
tBA
tHZB
tLZB
UT62V25616(I)-70
MIN.
MAX.
70
-
-
70
-
70
-
35
10
-
5
-
-
25
-
25
5
-
-
70
-
30
0
-
UT62V25616(I)-100
MIN.
MAX.
100
-
-
100
-
100
-
50
10
-
5
-
-
30
-
30
5
-
-
100
-
40
0
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62V25616(I)-70
MIN.
MAX.
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
LB , UB Valid to End of Write
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
tBW
70
-
60
-
60
-
0
-
55
-
0
-
30
-
0
-
5
-
-
30
60
-
*These parameters are guaranteed by device characterization, but not production tested.
UT62V25616(I)-100
MIN.
MAX.
100
-
80
-
80
-
0
-
70
-
0
-
40
-
0
-
5
-
-
40
80
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P80067
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