IDT54FCT162H272ATE 查看數據表（PDF） - Integrated Device Technology
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IDT54FCT162H272ATE Datasheet PDF : 8 Pages
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IDT54/74FCT162H272AT/CT/ET
FAST CMOS 12-BIT SYNCHRONOUS TRI-PORT BUS EXCHANGER
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
VIN
Pulse
Generator
V OUT
D.U.T.
500Ω
50pF
500Ω
RT
CL
MILITARY AND COMMERCIAL TEMPERATURES RANGES
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
3032 tbl 11
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
3071 lnk 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
t SU
tH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tW
1.5V
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
t REM
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
t SU
3V
1.5V
0V
3071 lnk 05
3071 lnk 06
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
t PLH
t PLH
t PHL
t PHL
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
V OL
3V
1.5V
0V
3071 lnk 07
ENABLE
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
3071 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.5
7
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