LY62L5128WL(2016) 查看數據表（PDF） - Lyontek Inc.

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LY62L5128WL
(Rev.:2016)

512K X 8 BIT LOW POWER CMOS SRAM

Lyontek Inc. 



Rev. 1.14

LY62L5128

512K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

Address

Dout

tRC

tAA

Previous Data Valid

tOH

Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

Address

CE#

OE#

Dout

tRC

tAA

tACE

High-Z

tOE

tOLZ

tCLZ

tOH

tOHZ

tCHZ

Data Valid

High-Z

Notes :

1.WE# is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low.

3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.

4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.

Lyontek Inc. reserves the rights to change the specifications and products without notice.

2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

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