NL37WZ07MU1TCG 查看數據表（PDF） - ON Semiconductor

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NL37WZ07MU1TCG

Triple Buffer with Open Drain Outputs

ON Semiconductor 

NL37WZ07

OPEN

2 x VCC

GND

R1

DUT

RT

RL

OUTPUT

CL*

Test

Switch

Position

tPLH / tPHL Open

tPLZ / tPZL 2 x VCC

tPHZ / tPZH GND

X = Don’t Care

CL, pF

RL, W R1, W

See AC Characteristics Table

50

500 500

50

500 500

CL includes probe and jig capacitance

RT is ZOUT of pulse generator (typically 50 W)

f = 1 MHz

Figure 3. Test Circuit

tr = 3 ns

INPUT

10%

OUTPUT

OUTPUT

90%

Vmi

90%

Vmi

tf = 3 ns

VCC

10%

GND

tPHL

tPLH

VOH

Vmo

Vmo

tPLH

tPHL

VOL

VOH

Vmo

Vmo

VOL

INPUT

OUTPUT

OUTPUT

Vmi

tPZL

Vmo

tPZH

Vmo

Figure 4. Switching Waveforms

Vmi

tPLZ

VCC

GND

~VCC

VOL + VY

VOL

tPHZ

VOH

VOH − VY

~0 V

VCC, V

1.65 to 1.95

2.3 to 2.7

3.0 to 3.6

4.5 to 5.5

Vmi, V

VCC/2

VCC/2

VCC/2

VCC/2

tPLH, tPHL

VCC/2

VCC/2

VCC/2

VCC/2

Vmo, V

tPZL, tPLZ, tPZH, tPHZ

VCC/2

VCC/2

VCC/2

VCC/2

VY, V

0.15

0.15

0.3

0.3

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