WED9LAPC2C16V4BC
FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @ CAS LATENCY = 3,
BURST LENGTH = 1
0
1
2
3
4
5
GCLK
tCC
tCH
tCL
tSS
VCRAS
tRCD
tSH
VCCAS
tSS
tSH
tSS
tSH
VCADDR
Ra
Ca
6
7
8
9
10 11
tRCD
tRAS
tCCD
tSS
tSH
Cb
Cc
12 13 14 15 16 17 18 19
tRP
Rb
VCBS
BS
VCADDR9/AP
Ra
VCDATA
VCWE
VCDQM
BS
BS
BS BS
tRAC
tSAC
tSLZ
tSS
tSH
Qa
Db
tOH
tSS
tSH
tSS
tSH
BS
Rb
Qc
Row Active
Read
Write
Read
Precharge
Row Active
DON’T CARE
July 2000 Rev. 0
11
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