WT21-A-HCI 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

WT21-A-HCI

BLUETOOTH HCI MODULE

Unspecified 

7.1.2 CSPI Register Write Cycle

The command and address are locked into the slave, followed by 16bits of write data. An Error

Byte is returned on the MISO signal indicating whether or not the transfer has been successful.

Figure 9: CSPI Register Write Cycle

7.1.3 CSPI Register Read Cycle

The command and address field are clocked into the slave, the slave then returns the following:



Bytes of badding data (MISO held low)



Error byte



16-bits of read data

Figure 10: CSPI Register Read Cycle

7.1.4 CSPI Register Burst Write Cycle

Burst transfers are used to access the MMU buffers. They cannot be used to access registers.

Burst read/write cycles are selected by setting the nRegister/Burst bit in the command field to

1.

Burst transfers are byte orientated, have a minimum length of 0 bytes and a maximum length

of 64kbytes. Setting the length field to 0 results in no data being transferred to or from the

MMU.

As with a register access, the command and address fields are transferred first. There is an

optional length field transferred after the address. The use of the length field is controlled by

the LengthFieldPresent bit in the Function 0 registers, which is cleared on reset.

Figure 11: CSPI Burst Write Cycle

Bluegiga Technologies Oy

Page 24 of 56

Share Link: