PI6C2309-1HW 查看數據表（PDF） - Pericom Semiconductor Corporation
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PI6C2309-1HW Datasheet PDF : 6 Pages
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PI6C2309-1 1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V Zero-Delay Buffer
Product Features
• Zero input-output propagation delay
• Less than 200ps input to output propagation delay
• Multiple low-skew outputs
– Output-output skew less than 250ps
– Device-device skew less than 700ps
– Two banks of four outputs and one ON-chip
– Internal feedback connection
• 10 MHz to 100 MHz operating range
• Low Jitter <200ps
• 3.3V operation
• High drive option (PI6C2309-1H)
• Temperature Rating: Commercial & Industrial
• Space-saving 16-pin, 150-mil SOIC package (W16)
and 16-pin TSSOP package (L16)
Functional Description
Providing two banks of four outputs, the PI6C2309-1 is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems.
The PI6C2309-1 provides 9 copies of a clock signal that has less than
200ps propagation delay compared to the reference clock. The skew
among the output clock signals for PI6C2309-1 is less than 250ps.
When there are no rising edges on the REF input, the PI6C2309-1
enters a power-down state. In this mode, the PLL is off and all
outputs are three-stated. This results in less than 50µA of current
draw.
The PI6C2309-1 has two banks of four outputs and a CLK_OUT that
can be controlled by the select inputs (see table below). If all output
clocks are not required, Bank B can be three-stated. For test
purposes or if the internal PLL is not needed, it can be bypassed.
Block Diagrams
FBK
PLL
MUX
REF
S2
Select Input
Decoding
S1
Pin Configuration PI6C2309-1
CLK_OUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
16
15
14
16-Pin 13
L, W
12
11
10
9
CLK_OUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Select Input Decoding for PI6C2309-1
S2
S1
CLKA[1-4]
0
0
Three-State
0
1
Driven
1
0
Driven
1
1
Driven
CLKB[1-4]
Three-State
Three-State
Driven
Driven
CLK_OUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
1
PS8478 04/27/00
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