BR24G04FJ-3A 查看數據表（PDF） - ROHM Semiconductor
零件编号
产品描述 (功能)
比赛名单
BR24G04FJ-3A Datasheet PDF : 36 Pages
| |||
BR24G04-3A
●Read Command
○ Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
SDA
LINE
S
W
T
R
A
I
R
SLAVE
T
T ADDRESS E
WORD
ADDRESS(n)
S
T
R
A
E
R
SLAVE
A
T ADDRESS D
S
T
O
DATA(n)
P
1 0 1 0 A2A1P0
WA
7
0
RA
/C
WK
WA
0
A
C
K
1 0 1 0 A2A1P0
D7
00
RA
/C
WK
D0
A
C
K
Figure 38. Random read cycle
SDA
LINE
S
T
R
A
E
R
SLAVE
A
T ADDRESS D
S
T
O
DATA(n)
P
1 0 1 0 A2A1P0
D7
0
RA
/C
WK
D0
A
C
K
Figure 39. Current read cycle
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
SDA
LINE
1 0 1 0 A2 A1P0
D7
D0
00
RA
A
/C
C
WK
K
S
T
DATA(n+x)
O
P
D7
D0
A
A
C
C
K
K
Figure 40. Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal
'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
www.rohm.com
© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
17/33
TSZ02201-0R2R0G100560-1-2
11.Jun.2019 Rev.004
Share Link: 