GA1086MC500 查看數據表（PDF） - TriQuint Semiconductor
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GA1086MC500 Datasheet PDF : 12 Pages
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GA1086
AC Specifications
Figure 11. Switching Waveforms
(Supply voltage: +5 V + 5%, Ambient temp: 0 °C to +70 °C) Buffer Configuration (FBIN = FBOUT)
Input Clocks
Min
FIN CLK frequency
30
tCP CLK period
14.9
tCPW CLK pulse width
3.0
tIR Input rise time (0.8 V – 2.0 V) —
Typ Max Unit
— 67 MHz
—
33
ns
— — ns
— 2.0 ns
REFCLK
FBIN
tCPW
t PD1,2
tCPW
Output Clocks
Min
tOR Output rise time (0.8 V – 2.0 V) 0.15
tOF Output fall time (0.8 V – 2.0 V) 0.15
tPD11 CLK Î to FBIN Î (MC500)
–850
tPD21,2 CLK Î to FBIN Î (MC1000)
–1350
tSKEW12,3 Q1–Q9 and FBOUT (0.8V)
–125
tSKEW12,3 Q1–Q9 and FBOUT (1.5V)
–125
tSKEW12,3 Q1–Q9 and FBOUT (2.0V)
–125
tSKEW22,3 Q/2 Output skew
—
tW 4 Output window
—
tCYC 5 Duty-cycle variation
—
tSYNC 6 Synchronization time
—
tJIT 7 Period-to-period jitter
—
Typ Max Unit
— 1.4 ns
— 1.4 ns
–350 +150 ps
–350 +650 ps
— +125 ps
— +125 ps
— +125 ps
0.6 1.2 ns
100 250 ps
1.0 — ns
200 500 µs
75 — ps
Q0 – Q10
(INDIVIDUALLY)
t PERIOD
t JP
Figure 12. AC Test Circuit
+5 V
R1
Z
R2
+5 V
R1
Z
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
Y
FBIN Q0
Q1
Q2
•
•
•
•
CLK Q10
50 Ω
X
•
•
•
•
t JR
+5 V
R1 +5 V
R2 R1
R2
+5 V
R1
R2
Notes: 1. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay tPD is measured at the 1.5 V level between CLK and FBIN.
2. tPD and tSKEW are tested with an input clock having a rise time of 0.5 ns (0.8 V to 2.0 V).
3. The output skew is measured from the middle of the output window, tW. The maximum skew is guaranteed across all voltages and
temperatures.
4. tW specifies the width of the window in which outputs Q1–Q9 switch.
5. This specification represents the deviation from 50/50 on the outputs; it is sampled periodically but is not guaranteed.
6. tSYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and a connection from one of the
outputs to FBIN.
7. Jitter is specified as a peak-to-peak value.
10
For additional information and latest specifications, see our website: www.triquint.com
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