GA1087 查看數據表（PDF） - TriQuint Semiconductor

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比赛名单

GA1087

11-Output Configurable Clock Buffer

TriQuint Semiconductor 

GA1087

Table 2. Test Mode Selection

Test

F0

F1

1

1

0

1

0

0

1

0

1

1

1

1

Mode

÷4

÷5

÷6

—

Ref. Clock

f REF

f REF

f REF

—

Group B:

Outputs Q0–Q4

f REF ÷ 8

f REF ÷ 10

f REF ÷ 12

—

Group A:

Outputs Q5–Q10

f REF ÷ 4␣ ␣

f REF ÷ 5

f REF ÷ 6

—

Layout Guidelines

Multiple ground and power pins on the GA1087 reduce

ground bounce. Good layout techniques, however, are

necessary to guarantee proper operation and to meet

the specifications across the full operating range.

TriQuint recommends bypassing each of the VDD supply

pins to the nearest ground pin, as close to the chip as

possible.

Figure 2. Top Layer Layout of Power Pins

(approx. 3.3x)

VDD

C4

Pin 1

VDD

C3

Figure 2 shows the recommended power layout for the

GA1087. The bypass capacitors should be located on

the same side of the board as the GA1087. The VDD

traces connect to an inner-layer VDD plane. All of the

ground pins (GND) are connected to a small ground

plane on the surface beneath the chip. Multiple through

holes connect this small surface plane to an inner-layer

ground plane. The capacitors (C1–C5) are 0.1 mF.

TriQuint’s test board uses X7R temperature-stable

capacitors in 1206 SMD cases.

Ground

Plane

Pin 15

C5

VDD

VDD

C2

C1

VDD

For additional information and latest specifications, see our website: www.triquint.com

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