CS5180-CL 查看數據表（PDF） - Cirrus Logic

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CS5180-CL

∆Σ Modulator & 8 kHz to 400 kHz 16-Bit ADC

Cirrus Logic 

CS5180

SWITCHING CHARACTERISTICS (TA = 0 °C to 70 °C; VA+ = 5 V ±5%, VD+ = 2.7 V to 5.5 V;

AGND = DGND = 0 V; MODE = VD+)

Parameter

Symbol Min

Master Clock Frequency

(Note 2) MCLK 0.512

Master Clock Duty Cycle

45

Rise Times

(Notes 2, 10, and 11) trise

Any Digital Input, Except MCLK

-

MCLK

-

Any Digital Output

-

Fall Times

(Notes 2, 10, and 11) tfall

Any Digital Input, Except MCLK

-

MCLK

-

Any Digital Output

-

Calibration/Sync

RESET rising to MCLK rising

-

RESET rising recognized, to FSO falling

-

SYNC rising to MCLK rising

-

SYNC rising recognized to FSO falling

-

PWDN rising recognized to FSO falling

-

SYNC high time

1/MCLK

RESET low time

1/MCLK

Serial Port Timing

(Note 12)

SCLK frequency

-

SCLK high time

SCLK low time

FSO falling to SCLK rising

SCLK falling to new data bit available

SCLK rising to FSO rising

t1

-

t2

-

t3

-

t4

-

t5

-

Typ

25.6

-

-

-

20

-

-

20

3

988205/MCLK

3

5161/MCLK

5168/MCLK

-

-

MCLK/3

1/MCLK

2/MCLK

2/MCLK + 2E-9

1.5

1/MCLK - 2E-9

Max Unit

26 MHz

55

%

100

ns

.2/MCLK s

-

ns

100

ns

.2/MCLK s

-

ns

-

ns

-

s

-

ns

-

s

-

s

-

s

-

s

-

Hz

-

s

-

s

-

s

-

ns

-

s

Notes: 10. Rise and Fall times are specified at 10% to 90% points on waveform.

11. RESET, SYNC, and PWDN have Schmitt-trigger inputs.

12. Specifications applicable to complementary signals SCLK and SDO.

FSO

t3

t1 t2

t5

SCLK

t4

SDATA XX MSB MSB-1

LSB-1 LSB XX

Figure 1. Serial Port Timing (not to scale)

7

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