MC10198 查看數據表（PDF） - ON Semiconductor
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MC10198 Datasheet PDF : 12 Pages
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MC10198
LOGIC DIAGRAM
VEE
VCC
6
4
REXT
CEXT
5
E pos
Q
3
7
EXTERNAL PULSE
WIDTH CONTROL
VCC1 = PIN 1
10
ENEG
VCC2 = PIN 16
VEE = PIN 8
13
TRIGGER
INPUT
15
HI-SPEED
Q
2
INPUT
DIP
PIN ASSIGNMENT
VCC1
Q
Q
CEXT
EPOS
REXT
EXT.PULSE
WIDTH CONTROL
VEE
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VCC2
HIGH-SPEED
INPUT
N/C
TRIGGER INPUT
N/C
N/C
ENEG
N/C
TRUTH TABLE
INPUT
OUTPUT
EPos
L
L
H
H
ENeg
L
H
L
H
Triggers on both positive & negative input slopes
Triggers on positive input slope
Triggers on negative input slope
Trigger is disabled
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
TABLE 1 — PRECONDITION SEQUENCE
0(Gnd)
w 10 ns
w 10 ns
-1.0
-2.0
-3.0
-4.0
-5.0
0
Pin 1
open
10
20
30
t(ns)
1. At t = 0 a.) Apply VIHmax to Pin 5 and 10.
b.) Apply VILmin to Pin 15.
c.) Ground Pin 4.
2. At t w 10 ns a.) Open Pin 1.
b.) Apply –3.0 Vdc to Pin 4.
Hold these conditions for
w10 ns.
3. Return Pin 4 to Ground and perform test as
indicated in Table 2.
TABLE 2 — CONDITIONS FOR TESTING OUTPUT LEVELS
(See Table 1 for Precondition Sequence)
VIH max
P1
VIL min
P2
Pins 1, 16 = VCC = Ground
Pins 6, 8 = VEE = –5.2 Vdc
Outputs loaded 50 Ω to –2.0 Vdc
VILA max
VIL min
VIHA max
P3
VIL min
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