MK2731-04S 查看數據表（PDF） - Integrated Circuit Systems
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MK2731-04S Datasheet PDF : 4 Pages
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PRELIMINARY INFORMATION
MK2731-04C
MPEG Audio Clock
Pin Assignment
MK2731-04
X2 1
X1 2
VDD 3
VDD 4
GND 5
GND 6
GND 7
S2 8
16 DC
15 DC
14 S0
13 S1
12 DC
11 CLK2
10 VDD
9 CLK1
16 pin narrow (150 mil) SOIC
Output Clocks Select Table (MHz)
S2
Pin 8
0
0
0
0
1
1
1
1
S1
Pin 13
0
0
1
1
0
0
1
1
S0
Pin 14
0
1
0
1
0
1
0
1
CLK1 CLK2
Pin 9 Pin 11
16.9344 33.8688
11.2896 22.5792
8.192 16.384
18.432 36.864
11.2896 22.5792
12.288 24.576
Test Test
Test Test
Key: 0 = connect directly to GND
1 = connect directly to VDD
Pin Descriptions
Number
1
2
3, 4, 10
5, 6, 7
8
9
11
12, 15, 16
13
14
Name
X2
X1
VDD
GND
S2
CLK1
CLK2
DC
S1
S0
Type
XO
XI
P
P
I
O
O
-
I
I
Description
Crystal connection. Connect to a parallel mode 14.4 MHz crystal.
Crystal connection. Connect to a parallel mode 14.4 MHz crystal.
Connect to +3.3V or +5V. Must be same at all VDDs.
Connect to ground.
Frequency select pin 2. Determines clock outputs per table above.
Clock output 1 set by status of S0-S2. See table above. This output is CLK2/2
Clock output 2 set by status of S0-S2. See table above.
Don't Connect. Do not connect anything to these pins.
Frequency select pin 1. Determines clock outputs per table above.
Frequency select pin 0. Determines clock outputs per table above.
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, XO = crystal
connections
External Components
The MK2731-04 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 3 and 5, and VDD and GND
on pins 10 and 6, as close to the MK2731-04 as possible. Other VDDs can be connected to pin 10. A series
termination resistor of 33 Ω may be used for each clock output. Any unused clock outputs should be left
unconnected (DC, floating). The input crystal must be connected as close to the chip as possible. The input
crystal should be fundamental mode, parallel resonant. For accurate outputs, the crystal should be tuned
with two identical capacitors to ground, as shown on the block diagram. The value of these two crystal caps
should be equal to (CL-6)*2, where CL is the crystal load (or correlation) capacitance.
MDS 2731-04 CA
2
Revision 122799
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
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