Q67100-H5092 查看數據表（PDF） - Infineon Technologies

零件编号

产品描述 (功能)

比赛名单

Q67100-H5092

Nonvolatile Memory 1-Kbit E2PROM

Infineon Technologies 

SDA 2516-5

Figure 2

Timing Conditions for the I2C Bus (high-speed mode)

Parameter

Minimum time the bus must be free

before a new transmission can start

Start condition hold time

Clock low period

Clock high period

Start condition set-up time,

only valid for repeated start code

Data set-up time

Rise time of both the SDA- and SCL-line

Fall time of both the SDA- and SCL-line

Stop condition set-up time

Hold time data

Symbol

Limit Values

min.

max.

tBUF

4.7

tHD; STA 4.0

tLOW

4.7

tHIGH

4.0

tSU; STA 4.7

tSU; DAT 250

tR

1

tF

300

tSU; SPO 4.7

tHD; DAT 0*)

Unit

µs

µs

µs

µs

µs

ns

µs

ns

µs

*) Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns)

of the falling edge of SCL.

Semiconductor Group

14

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