P4C164-10JI 查看數據表（PDF） - Performance Semiconductor
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P4C164-10JI Datasheet PDF : 8 Pages
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READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
(9)
t RC
ADDRESS
DATA OUT
t AA
t OH
PREVIOUS DATA VALID
P4C164/164L
DATA VALID
READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
tRC
CE 1
CE 2
DATA OUT
I CC
VCC SUPPLY
CURRENT I SB
tAC (10)
(8,10)
t LZ
(10)
t PU
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
t HZ(8,10)
DATA VALID
t
(10)
PD
HIGH IMPEDANCE
10. Transitions caused by a chip enable control have similar delays
irrespective
of
whether
CE
1
or
CE2
causes
them.
95
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