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产品描述 (功能) : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   LOW input to CD (Clear) sets Q to LOW level
   Clear and Set are independent of clock
   Simultaneous LOW on CD and SD makes both Q and Q HIGH
  
• Outputs Source/Sink 24 mA
• ′ACT112 Has TTL Compatible Inputs

产品描述 (功能) : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

The MC74AC113/74ACT113 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.

Asynchronous Inputs:
   LOW input to SD (Set) sets Q to HIGH level
   Set is independent of clock
• Outputs Source/Sink 24 mA
• ′ACT113 Has TTL Compatible Inputs

产品描述 (功能) : Dual JK POSITIVE edge-triggered flip-flop

Dual JK POSITIVE edge-triggered flip-flop

The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.

产品描述 (功能) : Dual JK flip-flop with set and reset; positive-edge-trigger

General description
The 74HC109; 74HCT109 is a Dual positive edge triggered JK flip-flop featuring indiviDual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits
■ Input levels:
    ◆ For 74HC109: CMOS level
    ◆ For 74HCT109: TTL level
■ J and K inputs for easy D-type flip-flop
■ Toggle flip-flop or “do nothing” mode
■ Specified in compliance with JEDEC standard no. 7A
■ ESD protection:
    ◆ HBM JESD22-A114F exceeds 2000 V
    ◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Philips
Philips Electronics
产品描述 (功能) : Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT109 are Dual positive-edge triggered, JK flip-flops with indiviDual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

FEATURES
• J, K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Output capability: standard
• ICC category: flip-flops

产品描述 (功能) : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop LOW POWER SCHOTTKY

The SN54/74LS107A is a Dual JK flip-flop with indiviDual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOWtransition of the clock. A LOW signal on CD input overrides the other inputs and makes the Q output LOW. The SN54 /74LS107A is the same as the SN54/74LS73A but has corner power pins.

Motorola
Motorola => Freescale
产品描述 (功能) : Dual JK POSITIVE edge-triggered flip-flop

Dual JK POSITIVE edge-triggered flip-flop LOW POWER SCHOTTKY

The SN54/74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise andfall times of the clock waveform. The JKdesignallows operation as a D flip-flop by simply connecting the J and Kpins together.

产品描述 (功能) : AC Feedthrough Filters – Class Y2

FFA Series

• AC feedthrough filters
• Current Ratings from 10 to 300A
• Designed to meet the very stringent safety requirements of EN133200 class Y2 including the 5000V pulse test
• Custom versions available

Motorola
Motorola => Freescale
产品描述 (功能) : Dual JK negative edge-triggered flip-flop

Dual JK negative edge-triggered flip-flop

The SN54 /74LS113A offers indiviDual J, K, set, and clock inputs. These monolithic Dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum setup times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

Philips
Philips Electronics
产品描述 (功能) : Dual J-K positive edge-triggered flip-flop ith set and reset

DESCRIPTION
The 74ALS109A is a Dual positive edge-triggered JK-type flip-flop featuring indiviDual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation.

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