IDT71V509S66Y 查看數據表（PDF） - Integrated Device Technology
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IDT71V509S66Y
Integrated Device Technology
IDT71V509S66Y Datasheet PDF : 9 Pages
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IDT71V509
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBT™ AND FLOW-THROUGH OUTPUT
TIMING WAVEFORM OF READ AND WRITE CYCLES(1)
CLK
CEN
tSE tHE
tSA tHA
ADDRESS
A1
A2
A3
A4
A5
tSW tHW
WE
tSC tHC
CS
COMMERCIAL TEMPERATURE RANGE
A6
A7
A8
OE
DATA_in
DATA_out
tCD
tCHZ
D1
tSD tHD
D2
NOTES:
1. Dx represents the data for address Ax.
2. DATA_in and DATA_out together represent I/O(7:0).
D3
tCLZ
tCDC
tCD
D4
D5
D6
D7
3618 drw 06
TIMING WAVEFORM OF CEN OPERATION(1)
CLK
CEN
ADDRESS
A1
A3
WE
CS
OE
DATA_in
DATA_out
D1
D1
NOTES:
1. Dx represents the data for address Ax.
2. DATA_in and DATA_out together represent I/O(7:0).
11.3
A5
A6
A7
D3
D6
D5
3618 drw 07
8
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