GS71116J 查看數據表（PDF） - Giga Semiconductor

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GS71116J

64K x 16 1Mb Asynchronous SRAM

Giga Semiconductor 

GS71116TP/J/U

Write Cycle 1: WE control

Address

OE

CE

UB, LB

WE

Data In

Data Out

Write Cycle 2: CE control

Address

OE

CE

UB, LB

WE

Data In

Data Out

tWC

tAW

tWR

tCW

tBW

tAS

tWP

tWHZ

tDW tDH

Data valid

tWLZ

High impedance

tWC

tAW

tWR1

tAS

tCW

tBW

tWP

tDW tDH

Data valid

High impedance

Rev: 1.06 6/2000

9/15

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 1999, Giga Semiconductor, Inc.

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