W83194R-58A 查看數據表（PDF） - Winbond

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W83194R-58A

100MHZ AGP CLOCK FOR VIA CHIPSET

Winbond 

W83194R-58A

3.0 BLOCK DIAGRAM

PLL2

~

X1

XTAL

X2

OSC

¡Ò2

STOP

*FS(0:2) 3

*MODE

CPU3.3#_2.5

*SD_SEL#

CPU_STOP#

PCI_STOP#

*SDATA

*SCLK

PLL1

Spread

Spectrum

STOP

CPU_STOP#

LATCH

~5

POR

PCI

clock STOP

Divder

Control

Logic

Config.

Reg.

PCI_STOP#

PRELIMINARY

48MHz

24MHz

REF(0:1

2)

AGP(0:1)

2

CPUCLK(0:3)

4

SDRAM(0:11)

12

3

PCICLK(0:4)

5

PCICLK_F

4.0 PIN CONFIGURATION

Publication Release Date: Nov. 1999

-2-

Revision 0.30

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