M95320-MB3 查看數據表（PDF） - STMicroelectronics

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产品描述 (功能)

比赛名单

M95320-MB3

32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock

STMicroelectronics 

M95640, M95320

Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set pri-

or to each WRITE and WRSR instruction. The only

way to do this is to send a Write Enable instruction

to the device.

As shown in Figure 8., to send this instruction to

the device, Chip Select (S) is driven Low, and the

bits of the instruction byte are shifted in, on Serial

Data Input (D). The device then enters a wait

state. It waits for a the device to be deselected, by

Chip Select (S) being driven High.

Figure 8. Write Enable (WREN) Sequence

S

01234567

C

Instruction

D

High Impedance

Q

AI02281E

Write Disable (WRDI)

One way of resetting the Write Enable Latch

(WEL) bit is to send a Write Disable instruction to

the device.

As shown in Figure 9., to send this instruction to

the device, Chip Select (S) is driven Low, and the

bits of the instruction byte are shifted in, on Serial

Data Input (D).

Figure 9. Write Disable (WRDI) Sequence

The device then enters a wait state. It waits for a

the device to be deselected, by Chip Select (S) be-

ing driven High.

The Write Enable Latch (WEL) bit, in fact, be-

comes reset by any of the following events:

– Power-up

– WRDI instruction execution

– WRSR instruction completion

– WRITE instruction completion.

S

01234567

C

Instruction

D

High Impedance

Q

AI03750D

14/42

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