SAA7110 查看數據表（PDF） - Philips Electronics
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SAA7110 Datasheet PDF : 76 Pages
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Philips Semiconductors
One Chip Front-end 1 (OCF1)
Product specification
SAA7110; SAA7110A
9 FUNCTIONAL DESCRIPTION
9.1 Analog input processing (see Fig.5)
The SAA7110; SAA7110A offers six analog signal inputs,
two analog main channels with clamping circuit, analog
amplifier, anti-alias filter and video CMOS ADC. A third
analog channel also with clamping circuit, analog amplifier
and anti-alias filter can be added or switched to both main
channels directly before the ADCs.
9.2 Analog control circuits
The clamping control circuit controls the correct clamping
of the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. The normal
digital clamping level for luminance or CVBS signals is 64
and for chrominance signals is128.
The gain control circuits generate via I2C-bus the static
gain levels for the three analog amplifiers or controls one
of these amplifiers automatically via a built-in Automatic
Gain Control (AGC). The AGC is used to amplify a
CVBS or Y signal to the required signal amplitude,
matched to the ADCs input voltage range.
The anti-alias filters are adapted to the clock frequency.
The vertical blanking control circuit generates an I2C-bus
programmable vertical blanking pulse. During the vertical
blanking time gain and clamping control are frozen.
The fast switch control circuit is used for special
applications.
9.2.1 CLAMPING
The coupling capacitor is used as clamp capacitance for
each input. An internal digital clamp comparator generates
the information concerning clamp-up or clamp-down. The
clamping levels for the two ADC channels are adjustable
over the 8-bit range (1 to 254). Clamping time in normal
use is set with the HCL pulse at the back porch of the video
signal. The clamping pulse HCL is user adjustable.
9.2.2 GAIN CONTROL (see Fig.4)
The luminance AGC can be used for every channel were
luminance or CVBS is being received. AGC active time is
the sync tip of the video signal. The sync tip pulse HSY is
user adjustable. The AGC can be switched off and the gain
for the three main input channels can be adjusted
independently. Signal (white) peak control limits the gain
at signal overshoots. The flow charts (see Figs 8 and 9)
show more details of the AGC. The influence of supply
voltage variation within the specified range is automatically
eliminated by clamp and automatic gain control.
handbook, halfpaagnealog input level
+2.8 dB
0 dB
−6 dB
maximum
range 8.8 dB
minimum
controlled
ADC input level
0 dB
MGC823
Fig.4 Automatic gain control range.
9.3 Chrominance processing (see Fig.6)
The 8-bit chrominance signal passes the input interface,
the chrominance bandpass filter to eliminate DC
components, and is finally fed to the multiplication inputs
of a quadrature demodulator, where two subcarrier signals
from the local oscillator DTO1 with 90 degrees phase shift
are applied. The frequency is dependent on the present
colour standard.
The multiplier operates as a quadrature demodulator for all
PAL and NTSC signals; it operates as a frequency down
mixer for SECAM signals.
The two multiplier output signals are converted to a serial
UV data stream and applied to two low-pass filter stages,
then to a gain controlled amplifier. A final multiplexed
low-pass filter achieves, together with the preceding
stages, the required bandwidth performance.
The PAL and NTSC originated signals are applied to a
comb filter.
The signal originated from SECAM is fed through a Cloche
filter (0 Hz centre frequency), a phase demodulator and a
differentiator to obtain frequency demodulated colour
difference signals. The SECAM signal is fed after
de-emphasis to a cross-over switch, to provide both the
serial transmitted colour difference signals. These signals
are fed to the BCS control and finally to the output fomatter
stage and to the output interface.
1995 Oct 18
10
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