SAA7110 查看數據表（PDF） - Philips Electronics

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SAA7110

One Chip Front-end 1 (OCF1)

Philips Electronics 

Philips Semiconductors

One Chip Front-end 1 (OCF1)

Product specification

SAA7110; SAA7110A

SYMBOL

RESET

CGCE

VDD

VSS

HCL

HSY

HS

PLIN (HL)

ODD (VL)

VS

HREF

VSS

VDD

PIN

DESCRIPTION

32 Reset active LOW input/output (CGCE = 1, output; CGCE = 0, input); sets the device into a

defined state. All data outputs are in high impedance state. The I2C-bus is reset (waiting for

START condition). Using the external CGC, the LOW period must be maintained for at least

30 LLC clock cycles.

33 CGC Enable active HIGH input (CGCE = 1, on-chip CGC active; CGCE = 0, external CGC

mode, use SAA7197).

34 supply voltage (+5 V)

35 ground

36 Horizontal Clamping input/output pulse (programmable via I2C-bus bit PULIO: PULIO = 1,

output; PULIO = 0, input). This signal is used to indicate the black level clamping period for

the analog input interface. The beginning and end of its HIGH period (only in the output mode)

can be programmed via the I2C-bus registers 03H, 04H in 50 Hz mode and registers 16H,

17H in 60 Hz mode, active HIGH.

37 Horizontal Synchronization input/output indicator (programmable via I2C-bus bit PULIO:

PULIO = 1, output; PULIO = 0, input). This signal is fed to the analog interface. The beginning

and end of its HIGH period (only in the output mode) can be programmed via the I2C-bus

registers 01H, 02H in 50 Hz mode and registers 14H, 15H in 60 Hz mode, active HIGH.

38 Horizontal Synchronization output (programmable; the HIGH period is 128 LLC clock cycles).

The position of the positive slope is programmable in 8 LLC increments over a complete line

(64 µs) via the I2C-bus register 05H in 50 Hz mode or register 18H in 60 Hz mode.

39 PAL Identifier Not output; marks for demodulated PAL signals the inverted line (PLIN = LOW)

and a non-inverted line (PLIN = HIGH) and for demodulated SECAM the DR line

(PLIN = LOW) and the DB line (PLIN = HIGH). Select PLIN function via I2C-bus bit RTSE = 0.

(H-PLL locked output; a HIGH state indicates that the internal PLL has locked. Select HL

function via I2C-bus bit RTSE = 1).

40 ODD/EVEN field identification output; a HIGH state indicates the odd field. Select ODD

function via I2C-bus bit RTSE = 0.

(Vertical Locked output; a HIGH state indicates that the internal Vertical Noise Limiter (VNL)

is in a locked state. Select VL function via I2C-bus bit RTSE = 1).

41 Vertical Synchronization input/output (programmable via I2C-bus bit OEHV: OEHV = 1,

output; OEHV = 0, input). This signal indicates the vertical synchronization with respect to the

YUV output. The high period of this signal is approximately six lines if the VNL function is

active. The positive slope contains the phase information for a deflection controller, for

example the TDA9150. In input mode this signal is used to synchronize the vertical gain and

clamp blanking stage, active HIGH.

42 Horizontal Reference output; this signal is used to indicate data on the digital YUV-bus. The

positive slope marks the beginning of a new active line. The HIGH period of HREF is either

768 Y samples or 640 Y samples long depending on the detected field frequency

(50/60 Hz mode). HREF is used to synchronize data multiplexer/demultiplexers. HREF is also

present during the vertical blanking interval.

43 ground

44 supply voltage (+5 V)

1995 Oct 18

7

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