SM8213AM 查看數據表（PDF） - Nippon Precision Circuits
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SM8213AM Datasheet PDF : 33 Pages
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NIPPON PRECISION CIRCUITS INC.
SM8213AM
POCSAG Decoder For Multiframe Pagers
OVERVIEW
The SM8213AM is a POCSAG-standard (Post
Office Code Standardization Advisory Group) signal
processor LSI, which conforms to CCIR recommen-
dation 584 concerning standard international wire-
less calling codes.
The SM8213AM supports call messages in either
tone, numerical or character outputs at signal speeds
of 512, 1200 or 2400 bps. The signal input stage fea-
tures a built-in filter.
Each of the addresses (max. 7 + 1 dummy = 8) can
be assigned to any frame, which also makes the
device configurable for many additional services.
Each address can be independently set to ON/OFF.
Furthermore, built-in buffer memory means decoded
information can be fetched in sync with the micro-
controller clock, thereby reducing the microcontrol-
ler CPU time required. Intermittent-duty method
(battery saving (BS) method) control signals, com-
patible with PLL operation, and Molybdenum-gate
CMOS structure makes possible the construction of
low-voltage operation, low power dissipation sys-
tems.
The SM8213AM is available in 16-pin SSOPs.
FEATURES
s Conforms to POCSAG standard for pagers
s 512, 1200 or 2400 bps signal speed
s Multiframe compatible (each address individually
controllable)
s 8 addresses × 4 sub-addresses (total of 32
addresses) control
(8 addresses comprise 7 actual addresses + 1
dummy address)
s Built-in buffer memory (1 code word)
s Supports tone, numeric or character call messages
s Built-in input signal filter, with filter ON/OFF and
4 selectable filter characteristics
s PLL-compatible battery saving method (BS1,
BS2, BS3 outputs)
s BS1 (RF control main output signal) 61-step setup
time setting
s BS3 (PLL setup signal) 61-step setup time setting
s BS2 (RF DC-level adjustment signal) before/dur-
ing reception selectable adjustment timing
s 1-bit and 2-bit burst error auto-correction function
s 25 to 75% duty factor signal coverage
s 8 rate error detection condition settings
s 76.8 kHz system clock (crystal oscillator)
s 76.8 or 38.4 kHz clock output pin
s Built-in oscillator capacitor and feedback resistor
s 2.0 to 3.5 V operating supply voltage
s Molybdenum-gate CMOS process realizes low
power dissipation
s 16-pin SSOP
PINOUT
Top View
BS1 1
BS2
BS3
SIGNAL
XVSS
XT
XTN
VSS 8
16 VDD
ATTN
SDI
SDO
SCK
AREA
RSTN
9 CLKO
PACKAGE DIMENSIONS
Unit: mm
0.6TYP
6.8 0.3
0.36 0.1
0.8
0.15+-
0.10
0.05
0 10
0.4 0.2
NIPPON PRECISION CIRCUITS—1
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