MC145750VFU 查看數據表（PDF） - Motorola => Freescale

零件编号

产品描述 (功能)

比赛名单

MC145750VFU

QPSK Encoder

Motorola => Freescale 

DEVICE DESCRIPTION

π/4–Shift QPSK Encoding

RCR standard (STD–28) specifies the basic configuration

of this modulation scheme as shown in Figure 2. First, serial

data input is converted to Xk/Yk parallel streams. Then its

value is compared with one previous symbol Ik/Qk, respec-

tively, whether or not there is a change of polarity. If there is a

change, result is coded as 1. This two–bit πr (di–bit) is called

symbol, hence symbol rate is just half of the data input rate to

be modulated.

Phase transitions are determined as shown in Figure 3,

with respect to four di–bit values of Xk, Yk. (As is shown,

there should be at least π/4 of phase shift in each symbol tim-

ing unlike plain QPSK.) Actual in–phase outputs are fed to a

quadrature modulator circuit, and it is recommended that a

2– to 3–order LPF be used, which may be used as a level

shifter and dc offset compensation circuitry at the same time.

The reference voltage for the DACs is given by connecting

either of DAref1:3 to VDD according to the operating voltage

used. It is preferable not to have this voltage vary, since I/Q

output levels are affected.

Timing Generator

The PLL is intended in order to generate all required timing

signals for the devices. The VCO oscillating at the PN511

pattern rate is utilized when some characteristics are mea-

sured. By pulling MODE0 pin high, the device generates this

sequence. It is a useful simple measurement for the occu-

pied power bandwidth and the out–of–band power level. The

sequence itself can also be monitored at the PNO pin.

This circuit is reset by an external reset signal while the

low–state of DS is not valid for initializing the generator.

START–UP SEQUENCE

To ensure stability and to initialize the internal ROM and

encoder, the start–up sequence should be done at power–

up. Refer to Figure 4.

Di–Bit Input

Xk Yk Phase Shift

0

0

π/4

0

1

3π/4

1

0

– π/4

1

1

– 3π/4

Q

00

01

22.5°

I

11

10

Figure 3. Phase Diagram

VDD

REST/PDN

DS

90%

> 100 µs

1s

Figure 4. Start–Up Sequence

MOTOROLA

MC145750

7

Share Link: