ST16C454(1994) 查看數據表（PDF） - Exar Corporation

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ST16C454
(Rev.:1994)

QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

Exar Corporation 

ST16C454/68C454

REGISTER FUNCTIONAL DESCRIPTIONS

The following table delineates the assigned bit functions for the fifteen 454 internal registers. The assigned bit

functions are more fully defined in the following paragraphs.

Table 6, ST16C454 INTERNAL REGISTERS

A2 A1 A0

Register

[Default]

Note *5

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

General Register Set

000

RHR[XX]

bit-7

000

THR[XX]

bit-7

001

IER[00]

0

010

ISR[01]

0

011

LCR[00]

100

MCR[00]

divisor

latch

enable

0

101

LSR[60]

0

110

MSR[X0]

CD

111

SPR[FF]

bit-7

bit-6

bit-6

0

0

set

break

0

trans.

empty

RI

bit-6

bit-5

bit-5

0

0

set

parity

0

trans.

holding

empty

DSR

bit-5

bit-4

bit-4

0

0

even

parity

bit-3

bit-3

modem

status

interrupt

INT

priority

bit-2

parity

enable

bit-2

bit-2

receive

line

status

interrupt

INT

priority

bit-1

stop

bits

loop

back

break

interrupt

-OP2/

INTx

enable

framing

error

-OP1

parity

error

CTS

bit-4

delta

-CD

bit-3

delta

-RI

bit-2

bit-1

bit-1

transmit

holding

register

INT

priority

bit-0

word

length

bit-1

-RTS

overrun

error

delta

-DSR

bit-1

bit-0

bit-0

receive

holding

register

INT

status

word

length

bit-0

-DTR

receive

data

ready

delta

-CTS

bit-0

Special Register set: Note *2

000

DLL[XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-0

001

DLM[XX]

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

bit-9

bit-8

Note *2: The Special register set is accessible only when LCR bit-7 is set to “1”.

Rev. 3.20

14

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