ST16C454(1994) 查看數據表（PDF） - Exar Corporation

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ST16C454
(Rev.:1994)

QUAD UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

Exar Corporation 

ST16C454/68C454

at the top of the RHR.

LSR BIT-3:

Logic 0 = No framing error. (normal default condition)

Logic 1 = Framing error. The receive character did not

have a valid stop bit(s).

LSR BIT-4:

Logic 0 = No break condition. (normal default condi-

tion)

Logic 1 = The receiver received a break signal (RX

was a logic 0 for one character frame time).

LSR BIT-5:

This bit indicates that the 454 is ready to accept new

characters for transmission. This bit causes the 454 to

issue an interrupt to the CPU when the transmit

holding register is empty and the interrupt enable is

set.

Logic 0 = Transmit holding register is not empty.

(normal default condition)

Logic 1 = Transmit holding register is empty.

LSR BIT-6:

Logic 0 = Transmitter holding and shift registers are

full.

Logic 1 = Transmitter holding and shift registers are

empty (normal default condition).

LSR BIT-7:

Not used - Initialized to a logic 0.

Modem Status Register (MSR)

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the 454 is connected to. Four bits of this

register are used to indicate the changed information.

These bits are set to a logic 1 whenever a control input

from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

MSR BIT-0:

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the 454 has changed state

since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-1:

Logic 0 = No -DSR Change. (normal default condition)

Logic 1 = The -DSR input to the 454 has changed state

since the last time it was read. A modem Status

Interrupt will be generated.

MSR BIT-2:

Logic 0 = No -RI Change. (normal default condition)

Logic 1 = The -RI input to the 454 has changed from

a logic 0 to a logic 1. A modem Status Interrupt will be

generated.

MSR BIT-3:

Logic 0 = No -CD Change. (normal default condition)

Logic 1 = Indicates that the -CD input to the has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

MSR BIT-4:

-CTS (active high, logical 1). Normally MSR bit-4 bit

is the compliment of the -CTS input. However in the

loop-back mode, this bit is equivalent to the RTS bit in

the MCR register.

MSR BIT-5:

DSR (active high, logical 1). Normally this bit is the

compliment of the -DSR input. In the loop-back mode,

this bit is equivalent to the DTR bit in the MCR register.

MSR BIT-6:

RI (active high, logical 1). Normally this bit is the

compliment of the -RI input. In the loop-back mode

this bit is equivalent to the OP1 bit in the MCR register.

MSR BIT-7:

CD (active high, logical 1). Normally this bit is the

compliment of the -CD input. In the loop-back mode

this bit is equivalent to the OP2 bit in the MCR register.

Scratchpad Register (SPR)

The ST16C454 provides a temporary data register to

store 8 bits of user information.

Rev. 3.20

18

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